具有三态输出的 32 位边沿 D 类触发器 96-LFBGA -40 to 85
This 32-bit edge-triggered D-type flip-flop is designed for 1.65-V to 3.6-V VCC operation.
The SN74ALVCH32374 is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. It can be used as four 8-bit flip-flops, two 16-bit flip-flops, or one 32-bit flip-flop. On the positive transition of the clock CLK input, the Q outputs of the flip-flop take on the logic levels at the data D inputs. The output-enable OE\ input can be used to place the eight outputs in either a normal logic state high or low logic levels or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines without need for interface or pullup components.
OE\ does not affect internal operations of the flip-flop. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.
型号 | 品牌 | 下载 |
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74ALVCH32374ZKER | TI 德州仪器 | 下载 |
74ALVC244PW,118 | NXP 恩智浦 | 下载 |
74ALVC164245DGG,11 | NXP 恩智浦 | 下载 |
74ALVC164245DL,118 | NXP 恩智浦 | 下载 |
74ALVC16244DGG | Philips 飞利浦 | 下载 |
74ALS08MX | Fairchild 飞兆/仙童 | 下载 |
74ALS245ASJX | Fairchild 飞兆/仙童 | 下载 |
74ALVCH16244DGG-T | NXP 恩智浦 | 下载 |
74ALVC164245DL | NXP 恩智浦 | 下载 |
74ALVC164245DGG | NXP 恩智浦 | 下载 |
74ALVCH162373ZQLR | TI 德州仪器 | 下载 |