SN65LVDS95DGGR

LVDS SERDES发送器 LVDS SERDES TRANSMITTER

DESCRIPON

The SN65LVDS95 LVDS serdes serializer/deserializer transmitter contains three 7-bit parallel-load serial-out shift registers, a 7× clock synthesizer, and four low-voltage differential signaling LVDS line drivers in a single integrated circuit. These functions allow 21 bits of single-ended LVTTL data to be synchronously transmitted over 4 balanced-pair conductors for receipt by a compatible receiver, such as the SN65LVDS96.

FEATURES

• 3:21 Data Channel Compression at up to 1.428 Gigabits/s Throughput

• Suited for Point-to-Point Subsystem Communication With Very Low EMI

• 21 Data Channels Plus Clock in Low-Voltage TTL and 3 Data Channels Plus Clock Out Low-Voltage Differential

• Operates From a Single 3.3-V Supply and 250 mW Typ

• 5-V Tolerant Data Inputs

• "LVDS95 Has Rising Clock Edge Triggered Inputs

• Bus Pins Tolerate 6-kV HBM ESD

• Packaged in Thin Shrink Small-Outline Package With 20 Mil Terminal Pitch

• Consumes <1 mW When Disabled

• Wide Phase-Lock Input Frequency Range 20 MHz to 68 MHz

• No External Components Required for PLL

• Inputs Meet or Exceed the Requirements of ANSI EIA/TIA-644 Standard

• Industrial Temperature Qualified TA = –40°C to 85°C

• Replacement for the National DS90CR215