SRAM Chip Sync Single 2.5V 18M-Bit 1M x 18 3.2ns 119Pin BGA T/R
* 512K x 36, 1M x 18 memory configurations * Supports high performance system speed - 200 MHz 3.2 ns Clock-to-Data Access * ZBTTM Feature - No dead cycles between write and read cycles * Internally synchronized output buffer enable eliminates the need to control OE * Single R/W READ/WRITE control pin * Positive clock-edge triggered address, data, and control signal registers for fully pipelined applications * 4-word burst capability interleaved or linear * Individual byte write BW1 - BW4 control May tie active * Three chip enables for simple depth expansion * 2.5V power supply ±5% * 2.5V I/O Supply VDDQ * Power down controlled by ZZ input * Boundary Scan JTAG Interface IEEE 1149.1 Compliant * Packaged in a JEDEC standard 100-pin plastic thin quad flatpack TQFP, 119 ball grid array BGA
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|---|---|---|
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