SN74AUP1G126

具有三态输出的低功耗单路总线缓冲器闸

The AUP family is ’s premier solution to the industry’s low-power needs in battery-powered portable applications. This family ensures a very low static and dynamic power consumption across the entire VCC range of 0.8 V to 3.6 V, resulting in an increased battery life. This product also maintains excellent signal integrity see Figure 1 and Figure 2.

This bus buffer gate is a single line driver with a 3-state output. The output is disabled when the output-enable OE input is low. This device has the input-disable feature, which allows floating input signals.

To ensure the high-impedance state during power up or power down, OE should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver.

NanoStar™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

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Available in the Texas Instruments NanoStar™ Package

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Low Static-Power Consumption

ICC = 0.9 µA Max

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Low Dynamic-Power Consumption

Cpd = 4 pF Typ at 3.3 V

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Low Input Capacitance Ci = 1.5 pF Typ

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Low Noise – Overshoot and Undershoot

<10% of VCC

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Input-Disable Feature Allows Floating Input Conditions

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Ioff Supports Partial-Power-Down Mode Operation

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Input Hysteresis Allows Slow Input Transition and

Better Switching Noise Immunity at Input

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Wide Operating VCC Range of 0.8 V to 3.6 V

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Optimized for 3.3-V Operation

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3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation

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tpd = 4.6 ns Max at 3.3 V

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Suitable for Point-to-Point Applications

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Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II

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ESD Performance Tested Per JESD 22−

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2000-V Human-Body Model

A114-B, Class II

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1000-V Charged-Device Model C101

NanoStar Is a trademark of Texas Instruments.