AD9287ABCPZRL7-100

ADC Quad Pipelined 100MSPS 8Bit Serial 48Pin LFCSP EP T/R

Product Details

The AD9287 is a quad, 8-bit, 100 MSPS analog-to-digital con- verter ADC with an on-chip sample-and-hold circuit designed for low cost, low power, small size, and ease of use. The product operates at a conversion rate of up to 100 MSPS and is optimized for outstanding dynamic performance and low power in applications where a small package size is critical.

The ADC requires a single 1.8 V power supply and LVPECL-/ CMOS-/LVDS-compatible sample rate clock for full performance operation. No external reference or driver components are required for many applications.

The ADC automatically multiplies the sample rate clock for the appropriate LVDS serial data rate. A data clock output DCO for capturing data on the output and a frame clock output FCO for signaling a new output byte are provided. Individual-channel power-down is supported and typically consumes less than 2 mW when all channels are disabled.

The ADC contains several features designed to maximize flexibility and minimize system cost, such as programmable clock and data alignment and programmable digital test pattern generation. The available digital test patterns include built-in deterministic and pseudorandom patterns, along with custom user- defined test patterns entered via the serial port interface SPI.

The AD9287 is available in an RoHS compliant, 48-lead LFCSP. It is specified over the industrial temperature range of −40°C to +85°C.

**Product Highlights**

1. Small Footprint. Four ADCs are contained in a small, space-saving package.

2. Low power of 133 mW/channel at 100 MSPS.

3. Ease of Use. A data clock output DCO is provided that operates at frequencies of up to 400 MHz and supports double data rate DDR operation.

4. User Flexibility. The SPI control offers a wide range of flexible features to meet specific system requirements.

5. Pin-Compatible Family. This includes the AD9219 10-bit, AD9228 12-bit, and AD9259 14-bit.

**

Applications

.

*

* Medical imaging and nondestructive ultrasound

* Portable ultrasound and digital beam-forming systems

* Quadrature radio receivers

* Diversity radio receivers

* Tape drives

* Optical networking

* Test equipment

### Features and Benefits

.

4 ADCs integrated into 1 package

.

133 mW ADC power per channel at 100 MSPS

.

SNR = 49 dB to Nyquist

.

ENOB = 7.85 bits

.

SFDR = 65 dBc to Nyquist

.

Excellent linearity

DNL = ±0.2 LSB typical

INL = ±0.2 LSB typical

.

Serial LVDS ANSI-644, default

.

Low power, reduced signal option similar to IEEE 1596.3

.

Data and frame clock outputs

.

295 MHz full-power analog bandwidth

.

2 V p-p input voltage range

.

1.8 V supply operation

.

Serial port control

Full-chip and individual-channel power-down modes

Flexible bit orientation

Built-in and custom digital test pattern generation

Programmable clock and data alignment

Programmable output resolution

Standby mode