ISPLSI2032E-110LJ44

LATTICE SEMICONDUCTOR  ISPLSI2032E-110LJ44  可编程逻辑芯片, CMOS ISP EEPLD, PLCC44

The is a High Density Programmable Logic Device contains 32 registers, 32 universal I/O pins, two dedicated input pins, three dedicated clock input pins, one dedicated global OE input pin and a global routing pool GRP. The GRP provides complete interconnectivity between all of these elements. The ispLSI 2032E features 5V in-system programmability and in-system diagnostic capabilities. The ispLSI 2032E offers non-volatile reprogrammability of the logic, as well as the interconnect to provide truly reconfigurable systems. The basic unit of logic on the ispLSI 2032E device is the Generic Logic Block GLB. The GLBs are labelled A0, A1 to A7. There are a total of eight GLBs in the ispLSI 2032E device. Each GLB is made up of four macrocells. Each GLB has 18 inputs, a programmable AND/OR/Exclusive OR array and four outputs which can be configured to be either combinatorial or registered. Inputs to the GLB come from the GRP and dedicated inputs.

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SuperFAST high density in-system

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Programmable logic - 1000 PLD GATES

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High performance E2CMOS® technology - 5V programmable logic core

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Increased manufacturing yields, reduced time-to-market and improved product quality

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Reprogram soldered devices for faster prototyping

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Offers the ease of use and fast system speed of PLDs

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Complete programmable device can combine glue logic and structured designs

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Enhanced pin locking capability

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Three dedicated clock input pins

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Synchronous and asynchronous clocks

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Programmable output slew rate control to minimize switching noise

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Flexible pin placement

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Optimized global routing pool provides global interconnectivity