IS61QDB24M18-300M3L

SRAM Chip Sync Dual 1.8V 72M-Bit 4M x 18 0.45ns 165Pin LFBGA

* 4Mx18 configuration available * On-chip Delay-Locked loop DLL for wide data valid window * Separate independent read and write ports with concurrent read and write operations * Synchronous pipeline read with EARLY write operation * Double Data Rate DDR interface for read and write input ports * Fixed 2-bit burst for read and write operations * Clock stop support * Two input clocks K and K# for address and control registering at rising edges only * Two output clocks C and C# for data output control * Two echo clocks CQ and CQ# that are delivered simultaneously with data * +1.8V core power supply and 1.5, 1.8V Vddq, used with 0.75, 0.9V Vref. HSTL input and output interface * Registered addresses, write and read controls, byte writes, data in, and data outputs * Full data coherency * Boundary scan using limited set of JTAG 1149.1 functions * Byte write capability * Fine ball grid array FBGA package 13mmx15mm and 15mmx17mm body size 165-ball 11 x 15 array * Programmable impedance output drivers via 5x user-supplied precision resistor.