MC100LVEL56

双差分2 ： 1多路复用器 Dual Differential 2:1 Multiplexer

The is a dual, fully differential 2:1 multiplexer. The differential data path makes the device ideal for multiplexing low skew clock or other skew sensitive signals. The device features both individual and common select inputs to address both data path and random logic applications. The differential inputs have special circuitry which ensures device stability under open input conditions. When both differential inputs are left open the D input will pull down to V. The Dbar input will bias around V pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to V as a switching reference voltage. V may also rebias AC coupled inputs. When used, decouple V via a 0.01 5F capacitor and limit current sourcing or sinking to 0.5 mA. When not used, V

Features

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440ps Typical Propagation Delays

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Separate and Common Select

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ESD Protection: >2 KV HBM

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The 100 Series Contains Temperature Compensation

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PECL Mode Operating Range: VCC = 3.0 V to 3.8 V with VEE = 0 V

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NECL Mode Operating Range: VCC = 0 V with VEE = -3.0 V to -3.8 V

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Internal Input 75 K ohm Pulldown Resistors

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Q Output will Default LOW with Inputs Open or at VEE

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Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test

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Flammability Rating: UL-94 code V-0 @ 1/8", Oxygen Index 28 to 34

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Transistor Count = 147 devices

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Pb-Free Packages are Available