18位总线接口触发器具有三态输出 18-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS
These 18-bit flip-flops feature 3-state outputs designed specifically for driving highly-capacitive or relatively low-impedance loads. They are particularly suitable for implementing wider buffer registers, I/O ports, parity bus interfacing, and working registers.
The "ACT16823 can be used as two 9-bit flip-flops or one 18-bit flip-flop. With the clock-enable input low, the D-type flip-flops enter data on the low-to-high transitions of the clock. Taking high disables the clock buffer, thus latching the outputs. Taking the clear input low causes the Q outputs to go low independently of the clock.
A buffered output-enable input can be used to place the outputs in either a normal logic state high or low logic levels or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly.
does not affect the internal operation of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.
The 74ACT16823 is packaged in the shrink small-outline package, which provides twice the I/O pin count and functionality of standard small-outline packages in the same printed-circuit-board area.
The 54ACT16823 is characterized for operation over the full military temperature range of 55°C to 125°C. The 74ACT16823 is characterized for operation from -40°C to 85°C
型号 | 品牌 | 下载 |
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74ACT16823DLR | TI 德州仪器 | 下载 |
74ACT16244DL | TI 德州仪器 | 下载 |
74ACT244MTC | Fairchild 飞兆/仙童 | 下载 |
74ACT244SC | Fairchild 飞兆/仙童 | 下载 |
74ACT244SCX | Fairchild 飞兆/仙童 | 下载 |
74ACT541MTC | Fairchild 飞兆/仙童 | 下载 |
74AC244SC | Fairchild 飞兆/仙童 | 下载 |
74ACT541SC | Fairchild 飞兆/仙童 | 下载 |
74ACT11244DW | TI 德州仪器 | 下载 |
74ACT245SCX | Fairchild 飞兆/仙童 | 下载 |
74AC245SCX | Fairchild 飞兆/仙童 | 下载 |