CMOS双路2宽2 -INPUT AND- OR- INVERT门 CMOS DUAL 2-WIDE 2-INPUT AND-OR-INVERT GATE
The is a CMOS dual 2-wide 2-input AND-OR-INVERT Gate contains a pair of AND-OR-INVERT gates, each consisting of two 2-input AND gates driving a 3-input NOR gate. Individual inhibit controls are provided for both A-O-I gates.
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tPHL - 90ns, tPLH - 125ns Medium-speed operation
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Individual inhibit controls
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Standardized symmetrical output characteristics
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100% Tested for quiescent current at 20V
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1µA Maximum input current
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2.5V at VDD = 15V Noise margin
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5V, 10V and 15V Parametric ratings
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Meets all requirements of JEDEC tentative standard No. 13B