SN74LV08ADBR

四路2输入正与门 QUADRUPLE 2-INPUT POSITIVE-AND GATES

description/ordering information

These quadruple 2-input positive-AND gates are designed for 2-V to 5.5-V VCC operation. The ’LV08A devices perform the Boolean function Y = A • B or Y = A + B in positive logic.

These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the  outputs, preventing damaging current backflow through the devices when they are powered down.

• 2-V to 5.5-V VCC Operation

• Max tpd of 7 ns at 5 V

• Typical VOLP Output Ground Bounce

   <0.8 V at VCC = 3.3 V, TA = 25°C

• Typical VOHV Output VOH Undershoot

   >2.3 V at VCC = 3.3 V, TA = 25°C

• Support Mixed-Mode Voltage Operation on All Ports

• Ioff Supports Partial-Power-Down Mode Operation

• Latch-Up Performance Exceeds 250 mA Per JESD 17

• ESD Protection Exceeds JESD 22

   − 2000-V Human-Body Model A114-A

   − 200-V Machine Model A115-A

   − 1000-V Charged-Device Model C101