ADF4193BCPZ-RL

低相位噪声，快速建立PLL频率合成器 Low Phase Noise, Fast Settling PLL Frequency Synthesizer

Product Details

The ADF4193 frequency synthesizer can be used to implement local oscillators in the upconversion and downconversion sections of wireless receivers and transmitters. Its architecture is specifically designed to meet the GSM/EDGE lock time requirements for base stations. It consists of a low noise, digital phase frequency detector PFD, and a precision differential charge pump. There is also a differential amplifier to convert the differential charge pump output to a single-ended voltage for the external voltage-controlled oscillator VCO.

The Σ-Δ-based fractional interpolator, working with the N divider, allows programmable modulus fractional-N division. Additionally, the 4-bit reference R counter and on-chip frequency doubler allow selectable reference signal REFIN frequencies at the PFD input. A complete phase-locked loop PLL can be implemented if the synthesizer is used with an external loop filter and a VCO. The switching architecture ensures that the PLL settles inside the GSM time slot guard period, removing the need for a second PLL and associated isolation switches. This decreases cost, complexity, PCB area, shielding, and characterization on previous ping-pong GSM PLL architectures.

**Applications**

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GSM/EDGE base stations

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PHS base stations

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Instrumentation and test equipment

### Features and Benefits

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New, fast settling, fractional-N PLL architecture

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Single PLL replaces ping-pong synthesizers

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Frequency hop across GSM band in 5 µs with phase settled by 20 µs

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0.5° rms phase error at 2 GHz RF output

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Digitally programmable output phase

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RF input range up to 3.5 GHz

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3-wire serial interface

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On-chip, low noise differential amplifier

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Phase noise figure of merit: –216 dBc/Hz

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Loop filter design possible using simPLL™

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Qualified for automotive applications