AD9520-5

12 LVPECL / 24 CMOS输出时钟发生器 12 LVPECL/24 CMOS Output Clock Generator

Product Details

The provides a multioutput clock distribution function with subpicosecond jitter performance, along with an on-chip PLL that can be used with an external VCO.

The AD9520-5 serial interface supports both SPI and I2C ports. An in-package EEPROM, which can be programmed through the serial interface, can store user-defined register settings for power-up and chip reset.

The AD9520-5 features 12 LVPECL outputs in four groups. Any of the 1.6 GHz LVPECL outputs can be reconfigured as two 250 MHz CMOS outputs. If an application requires LVDS drivers instead of LVPECL drivers, refer to the AD9522-5. Each group of three outputs has a divider that allows both the divide ratio from 1 to 32 and the phase offset or coarse time delay to be set.

The AD9520-5 is available in a 64-lead LFCSP and can be operated from a single 3.3 V supply. The external VCO can have an operating voltage of up to 5.5 V. A separate output driver power supply can be from 2.375 V to 3.465 V.

The AD9520-5 is specified for operation over the standard industrial range of −40°C to +85°C.

**Applications**

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Low jitter, low phase noise clock distribution

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Clock generation and translation for SONET, 10Ge, 10GFC, Synchronous Ethernet, OTU2/3/4

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Forward error correction G.710

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Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs

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High performance wireless transceivers

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ATE and high performance instrumentation

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Broadband infrastructures

### Features and Benefits

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Low phase noise, phase-locked loop PLL

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Optional external 3.3 V/5 V VCO/VCXO to 2.4 GHz

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1 differential or 2 single-ended reference inputs

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Accepts CMOS, LVDS, or LVPECL references to 250 MHz

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Accepts 16.62 MHz to 33.3 MHz crystal for reference input

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Optional reference clock doubler

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Reference monitoring capability

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Automatic/ manual reference holdover and reference switchover modes, with revertive switching

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Glitch-free switchover between references

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Automatic recovery from holdover

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Digital or analog lock detect, selectable

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Optional zero delay operation

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Twelve 1.6 GHz LVPECL outputs divided into 4 groups

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Each group of 3 outputs shares a 1-to-32 divider with phase delay

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Additive output jitter as low as 225 fs rms

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Channel-to-channel skew grouped outputs < 16 ps

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Each LVPECL output can be configured as 2 CMOS outputs for fOUT ≤ 250 MHz

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Automatic synchronization of all outputs on power-up

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Manual output synchronization available

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SPI- and I2C-compatible serial control port

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64-lead LFCSP

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Nonvolatile EEPROM stores configuration settings