NXP 74HC4020BQ 芯片, 14 级二进制纹波计数器, DHVQFN16
The is a 14-stage Binary Ripple Counter with a clock input, an overriding asynchronous master reset input MR and 12 buffered parallel outputs Q0 and Q3 to Q13. The counter advances on the high-to-low transition of clock. A high on MR clears all counter stages and forces all outputs low, independent of the state of clock. Each counter stage is a static toggle flip-flop. This device features reduced input threshold levels to allow interfacing to TTL logic levels. Inputs also include clamp diodes, this enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.