Quad Channel Quad ADC Pipelined 500MSPS 14Bit JESD204B 72Pin LFCSP EP T/R
GENERAL DESCRIPTION
The AD9694 is a quad, 14-bit, 500 MSPS analog-to-digital converter ADC. The device has an on-chip buffer and a sample-and-hold circuit designed for low power, small size, and ease of use. This device is designed for sampling wide bandwidth analog signals of up to 1.4 GHz. The AD9694 is optimized for wide input bandwidth, high sampling rate, excellent linearity, and low power in a small package.
FEATURES
JESD204B Subclass 1 coded serial digital outputs Lane rates up to 15 Gbps
1.66 W total power at 500 MSPS
415 mW per analog-to-digital converter ADC channel
SFDR = 82 dBFS at 305 MHz 1.80 V p-p input range
SNR = 66.8 dBFS at 305 MHz 1.80 V p-p input range
Noise density = −151.5 dBFS/Hz 1.80 V p-p input range
0.975 V, 1.8 V, and 2.5 V dc supply operation
No missing codes
Internal ADC voltage reference
Analog input buffer
On-chip dithering to improve small signal linearity
Flexible differential input range 1.44 V p-p to 2.16 V p-p 1.80 V p-p nominal
1.4 GHz analog input full power bandwidth
Amplitude detect bits for efficient AGC implementation
4 integrated wideband digital processors 48-bit NCO, up to 4 cascaded half-band filters
Differential clock input
Integer clock divide by 1, 2, 4, or 8
On-chip temperature diode
Flexible JESD204B lane configurations
APPLICATIONS
Communications
Diversity multiband, multimode digital receivers 3G/4G, W-CDMA, GSM, LTE, LTE-A
General-purpose software radios
Ultrawideband satellite receivers
Instrumentation
Radars
Signals intelligence SIGINT
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