MT48LC4M16A2TG-75

MT48LC4M16A2TG-75概述

DRAM Chip SDRAM 64Mbit 4Mx16 3.3V 54Pin TSOP-II Tray

SYNCHRONOUS DRAM

MT48LC16M4A2  – 4 Meg x 4 x 4 banks

MT48LC8M8A2  – 2 Meg x 8 x 4 banks

MT48LC4M16A2  – 1 Meg x 16 x 4 banks

FEATURES

• PC66-, PC100-, and PC133-compliant

• Fully synchronous; all signals registered on positive edge of system clock

• Internal pipelined operation; column address can be changed every clock cycle

• Internal banks for hiding row access/precharge

• Programmable burst lengths: 1, 2, 4, 8, or full page

• Auto Precharge, includes CONCURRENT AUTO PRECHARGE, and Auto Refresh Modes

• Self Refresh Modes: standard and low power

• 64ms, 4,096-cycle refresh

• LVTTL-compatible inputs and outputs

• Single +3.3V ±0.3V power supply

MT48LC4M16A2TG-75数据文档
型号 品牌 下载
MT48LC4M16A2TG-75

Micron 镁光

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MT48LC16M16A2P-6AIT:G

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MT48LC16M16A2P-6A:G

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MT48LC32M16A2P-75IT:C

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MT48LC64M8A2P-75:C

Alliance Memory 联盟记忆

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MT48LC32M16A2P-75:C TR

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MT48LC32M16A2P-75 IT:C TR

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MT48LC64M8A2P-75:C TR

Alliance Memory 联盟记忆

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MT48LC32M16A2TG-75:C

Alliance Memory 联盟记忆

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MT48LC64M8A2P-75IT:C TR

Alliance Memory 联盟记忆

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