LMK04110

具有级联 PLL 的时钟抖动清除器 48-WQFN -40 to 85

The LMK04100 family of precision clock conditioners provides jitter cleaning, clock multiplication and distribution without the need for high-performance VCXO modules.

When connected to a recovered system reference clock and a VCXO, the device generates 5 low jitter clocks in LVCMOS, LVDS, or LVPECL formats.

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Cascaded PLLatinum PLL Architecture

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PLL1Redundant Reference Inputs Loss of Signal

DetectionAutomatic and Manual Selection of

Reference Clock Input

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PLL2Phase Detector Rate up to 100 MHzInput

Frequency-DoublerIntegrated VCO

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Outputs

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LVPECL/2VPECL, LVDS, and

LVCMOS Formats

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Support Clock Rates up to 1080 MHz

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Five Dedicated Channel Divider Blocks

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Common Output Frequencies Supported:

30.72 MHz, 61.44 MHz, 62.5 MHz,

74.25 MHz, 75 MHz, 77.76 MHz, 100 MHz,

106.25 MHz, 125 MHz, 122.88 MHz,

150 MHz, 155.52 MHz, 156.25 MHz, 159.375 MHz,

187.5 MHz, 200 MHz,

212.5 MHz, 245.76 MHz, 250 MHz, 311.04 MHz,

312.5 MHz, 368.64 MHz,

491.52 MHz, 622.08 MHz, 625 MHz, 983.04 MHz

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MICROWIRE SPI Programming Interface

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Industrial Temperature Range: –40 to 85 °C

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3.15 V to 3.45 V Operation

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Package: 48 Pin WQFN 7.0 × 7.0 × 0.8 mm