ADCLK846BCPZ

ANALOG DEVICES  ADCLK846BCPZ  芯片, 差分扇出缓冲器, 1.2GHZ, LFCSP-24

The is a 12-output low-power clock Fan-out Buffer optimized for low jitter and low power operation. Possible configurations range from 6 LVDS to 12 CMOS outputs, including combinations of LVDS and CMOS outputs. Two control lines are used to determine whether fixed blocks of outputs are LVDS or CMOS outputs. The clock input accepts various types of single-ended and differential logic levels including LVPECL, LVDS, HSTL, CML and CMOS.

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Pin-programmable control

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Sleep mode

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54fs Integrated jitter 12kHz to 20MHz

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100fs Additive broadband jitter

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2ns Propagation delay LVDS

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135ps Output rise/fall LVDS

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65ps Output-to-output skew LVDS