MC100EP196

3.3V ECL可编程延迟芯片与FTUNE 3.3V ECL Programmable Delay Chip with FTUNE

The is a programmable delay chip PDC designed primarily for clock deskewing and timing adjustment. It provides programmably variable delay of a differential ECL input signal. It has similar architecture to the EP195 with the added feature of further tuneability in delay using the FTUNE pin. The FTUNE input takes an analog voltage from V to fine tune the output delay from 0 to 60 ps.

Features

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Maximum Frequency > 1.2 GHz Typical

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PECL Mode Operating Range: VCC = 3.0 V to 3.6 V with VEE = 0 V

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NECL Mode Operating Range: VCC = 0 V with VEE = -3.0 V to -3.6 V

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Open Input Default State

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Safety Clamp on Inputs

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A Logic High on the ENbar Pin Will Force Q to Logic Low

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D[0:10] Can Accept Either ECL, LVCMOS, or LVTTL Inputs

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VBB Output Reference Voltage

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Pb-Free Packages are Available