TMS320C6211B

定点数字信号处理器

The TMS320C62x™ DSPs including the TMS320C6211/C6211B devices compose one of the fixed-point DSP families in the TMS320C6000™ DSP platform. The TMS320C6211 C6211 and C6211B devices are based on the high-performance, advanced Veloci™ very-long-instruction-word VLIW architecture developed by Texas Instruments TI, making these DSPs an excellent choice for multichannel and multifunction applications.

With performance of up to 1333 million instructions per second MIPS at a clock rate of 167 MHz, the C6211/C6211B device offers cost-effective solutions to high-performance DSP programming challenges. The C6211/C6211B DSP possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. This processor has 32 general-purpose registers of 32-bit word length and eight highly independent functional units. The eight functional units provide six arithmetic logic units ALUs for a high degree of parallelism and two 16-bit multipliers for a 32-bit result. The C6211/C6211B can produce two multiply-accumulates MACs per cycle for a total of 333 million MACs per second MMACS. The C6211/C6211B DSP also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals.

The C6211/C6211B uses a two-level cache-based architecture and has a powerful and diverse set of peripherals. The Level 1 program cache L1P is a 32-Kbit direct mapped cache and the Level 1 data cache L1D is a 32-Kbit 2-way set-associative cache. The Level 2 memory/cache L2 consists of a 512-Kbit memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or combinations of the two.The peripheral set includes two multichannel buffered serial ports McBSPs, two general-purpose timers, a host-port interface HPI, and a glueless external memory interface EMIF capable of interfacing to SDRAM, SBSRAM and asynchronous peripherals.

The C6211/C6211B has a complete set of development tools which includes: a new C compiler, an assembly optimizer to simplify programming and scheduling, and a Windows™ debugger interface for visibility into source code execution.

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Excellent Price/Performance Digital Signal Processors DSPs: TMS320C62x™ TMS320C6211 and TMS320C6211B

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Eight 32-Bit Instructions/Cycle

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C6211, C6211B, C6711, and C6711B are Pin-Compatible

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150-, 167-MHz Clock Rates

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6.7-, 6-ns Instruction Cycle Time

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1200, 1333 MIPS

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Extended Temperature Device C6211B

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VelociTI™ Advanced Very Long Instruction Word VLIW C62x™ DSP Core C6211/11B

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Eight Highly Independent Functional Units:

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Six ALUs 32-/40-Bit

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Two 16-Bit Multipliers 32-Bit Results

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Load-Store Architecture With 32 32-Bit General-Purpose Registers

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Instruction Packing Reduces Code Size

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All Instructions Conditional

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Instruction Set Features

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Byte-Addressable 8-, 16-, 32-Bit Data

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8-Bit Overflow Protection

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Saturation

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Bit-Field Extract, Set, Clear

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Bit-Counting

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Normalization

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L1/L2 Memory Architecture

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32K-Bit 4K-Byte L1P Program Cache Direct Mapped

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32K-Bit 4K-Byte L1D Data Cache 2-Way Set-Associative

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512K-Bit 64K-Byte L2 Unified Mapped RAM/Cache Flexible Data/Program Allocation

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Device Configuration

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Boot Mode: HPI, 8-, 16-, and 32-Bit ROM Boot

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Endianness: Little Endian, Big Endian

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32-Bit External Memory Interface EMIF

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Glueless Interface to Asynchronous Memories: SRAM and EPROM

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Glueless Interface to Synchronous Memories: SDRAM and SBSRAM

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512M-Byte Total Addressable External Memory Space

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Enhanced Direct-Memory-Access EDMA Controller 16 Independent Channels

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16-Bit Host-Port Interface HPI

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Access to Entire Memory Map

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Two Multichannel Buffered Serial Ports McBSPs

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Direct Interface to T1/E1, MVIP, SCSA Framers

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ST-Bus-Switching Compatible

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Up to 256 Channels Each

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AC97-Compatible

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Serial-Peripheral-Interface SPI Compatible Motorola™

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Two 32-Bit General-Purpose Timers

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Flexible Phase-Locked-Loop PLL Clock Generator

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IEEE-1149.1 JTAG Boundary-Scan-Compatible

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256-Pin Ball Grid Array BGA Package GFN and ZFN Suffixes

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0.18-µm/5-Level Metal Process

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CMOS Technology

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3.3-V I/Os, 1.8-V Internal

TMS320C62x, VelociTI, and C62x are trademarks of Texas Instruments.

Motorola is a trademark of Motorola, Inc.

All trademarks are the property of their respective owners.

IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.