AD9571ACPZPEC-RL

时钟发生器及支持产品 10 Clock Outputs Ethernet

Product Details

The AD9571 provides a multioutput clock generator function comprising a dedicated PLL core that is optimized for Ethernet line card applications. The integer-N PLL design is based on the Analog Devices, Inc., proven portfolio of high performance, low jitter frequency synthesizers to maximize network performance. Other applications with demanding phase noise and jitter requirements also benefit from this part.

The PLL section consists of a low noise phase frequency detector PFD, a precision charge pump CP, a low phase noise voltage controlled oscillator VCO, and a preprogrammed feedback divider and output divider. By connecting an external crystal or reference clock to the REFCLK pin, frequencies up to 156.25 MHz can be locked to the input reference.

Each output divider and feedback divider ratio is prepro-grammed for the required output rates. No external loop filter components are required, thus conserving valuable design time and board space.

The AD9571 is available in a 40-lead 6 mm × 6 mm lead frame chip scale package and can be operated from a single 3.3 V supply. The operating temperature range is −40°C to +85°C.

### Features and Benefits

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Fully integrated VCO/PLL core

 0.17 ps rms jitter from 1.875 MHz to 20 MHz at 156.25 MHz

 0.41 ps rms jitter from 12 kHz to 20 MHz at 125 MHz

 Input crystal or clock frequency of 25 MHz

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Preset divide ratios for 156.25 MHz, 33.33 MHz,100 MHz, and 125 MHz

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Choice of LVPECL or LVDS output format

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Integrated loop filter

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6 copies of reference clock output

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Rates configured via strapping pins

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Space saving 6 mm × 6 mm 40-lead LFCSP

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0.48 W power dissipation LVDS operation

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See data sheet for additional features