SRAM Chip Sync Quad 3.3V 9M-bit 256K x 36 3.1ns 165Pin BGA
* 100 percent bus utilization * No wait cycles between Read and Write * Internal self-timed write cycle * Individual Byte Write Control * Single R/W Read/Write control pin * Clock controlled, registered address, data and control * Interleaved or linear burst sequence control using MODE input * Three chip enables for simple depth expansion and address pipelining * Power Down mode * Common data inputs and data outputs * CKE pin to enable clock and suspend operation * JEDEC 100-pin TQFP, 165-ball PBGA and 119-ball PBGA packages * Power supply: VDD 3.3V ± 5%, VDDQ 3.3V/2.5V ± 5% * JTAG Boundary Scan for PBGA packages * Industrial temperature available * Lead-free available
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