DSPIC33CH128MP502-I/2N

芯片, 16位数字信号控制器, 双核心, 128K 闪存, 16K+

System developers designing high-end embedded control applications can benefit from a new Digital Signal Controller DSC with two dsPIC DSC cores in a single chip. The dsPIC33CH has one core that is designed to function as a master while the other is designed as a slave. The slave core is useful for executing dedicated, time-critical control code while the master core is busy running the user interface, system monitoring and communications functions, customized for the end application. The dsPIC33CH is designed to facilitate independent code development for each core by separate design teams and allows seamless integration when they are brought together in one chip. The dsPIC33CH family is optimized for high-performance digital power, motor control and other high-end embedded applications requiring sophisticated algorithms.

.

Master Core 90 MIPS and Slave Core 100 MIPS Operation

.

Independent Peripherals for Master Core and Slave Core

.

4 x 12-bit 3.5 MSPS ADCs

.

High Speed PWMs with 250ps resolution, 12 Ch

.

Low-Power Management Modes Sleep, Idle, Doze

.

Simultaneous Debugging Support for Master and Slave Cores