TMS320C6748BZWTD4

TEXAS INSTRUMENTS  TMS320C6748BZWTD4  芯片, 数字信号处理器, 456MHZ, NFBGA-361

The is a fixed/floating-point Digital Signal Processor provides significantly lower power than other members of the TMS320C6000™ platform of DSPs. The device enables original-equipment manufacturers OEMs and original-design manufacturers ODMs to quickly bring to market devices with robust operating systems, rich user interfaces and high processor performance through the maximum flexibility of a fully integrated, mixed processor solution. The device DSP core uses a 2-level cache-based architecture. The level 1 program cache L1P is a 32kB direct mapped cache and the level 1 data cache is a 32kB 2-way, set-associative cache. The level 2 program cache consists of a 256KB memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache or combinations of the two. Although the DSP L2 is accessible by other hosts in the system, an additional 128kB of RAM shared memory.

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Dedicated 16-bit time-based counter with period and frequency control

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6 Single-edge outputs, 6 dual-edge symmetric outputs or 3 dual-edge asymmetric outputs

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Dead-band generation

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PWM Chopping by high-frequency carrier

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High-speed parallel interface to FPGAs and data converters

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Data width on both channels is 8- to 16-bit inclusive

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Single-data rate or dual-data rate transfers

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Supports multiple interfaces with START, ENABLE and WAIT controls

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Two multichannel buffered serial ports McBSPs

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One multichannel audio serial port McASP

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Dedicated interrupt controller

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Dedicated switched central resource

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Standard power-management mechanism

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Two multimedia card MMC/secure digital SD card interfaces with secure data I/O SDIO interfaces

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Hardware support for modulo loop operation

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Exceptions support for error detection and program redirection