NXP 74HC139N 芯片, 74HC CMOS逻辑器件
The is a dual 2-to-4 line Decoder or Demultiplexer decodes two binary weighted address inputs nA0, nA1 to four mutually exclusive outputs nY0 to nY3. Each decoder features an enable input nE. When nE is high all outputs are forced high. The enable input can be used as the data input for a 1-to-4 demultiplexer application. Inputs include clamp diodes that enable the use of current limiting resistors to interface inputs to voltages in excess of VCC. Suitable for memory decoding, data routing or code conversion.
ESD sensitive device, take proper precaution while handling the device.