TLV320AIC20IPFBRG4

对于TLV320AIC2x布局和接地指南 Layout and Grounding Guidelines for TLV320AIC2x

FEATURES

• Mono 16-Bit Oversampling Sigma-Delta A/D Converter

• Mono 16-Bit Oversampling Sigma-Delta D/A Converter

• Support Maximum Master Clock of 100 MHz to Allow the DSP Output Clock to be Used as a Master Clock

• Selectable FIR/IIR Filter With Bypassing Option

• Programmable Sampling Rate up to:

– Max 26 Ksps With On-Chip IIR/FIR Filter

– Max 104 Ksps With IIR/FIR Bypassed

• On-Chip FIR Produced 84-dB SNR for ADC and 92-dB SNR for DAC

• Smart Time Division Multiplexed SMARTDM™ Serial Port

– Glueless 4-Wire Interface to DSP

– Automatic Cascade Detection ACD Self-Generates Master/Slave Device Addresses

– Programming Mode to Allow On-the-Fly Reconfiguration

– Continuous Data Transfer Mode to Minimize Bit Clock Speed

– Support Different Sampling Rate for Each Device

– Turbo Mode to Maximize Bit Clock for Faster Data Transfer and Allow Multiple Serial Devices to Share the Same Bus

– Allows up to 16 Devices to be Connected to a Single Serial Port

• Host Port

– 2-Wire Interface

– Selectable I2C or S2C

• Differential and Single-Ended Analog Input/Output

• Built-In Analog Functions:

– Analog and Digital Sidetone

– Antialiasing Filter AAF

– Programmable Input and Output Gain Control PGA

– Microphone/Handset/Headset Amplifiers

– AIC12K has an 8-Ω Speaker Driver

– Power Management With Hardware/Software Power-Down Modes 30 µW

• Separate Software Control for ADC and DAC Power Down

• Fully Compatible With Common TMS320™ DSP Family and Microcontroller Power Supplies

– 1.65 V - 1.95 V Digital Core Power

– 1.1 V - 3.6 V Digital I/O

– 2.7 V - 3.6 V Analog

• Power Dissipation PD

– 11.2 mW at 3.3 V in Standard Operation

– 17.8 mW at 3.3 V With Headphone Drivers

• Internal Reference Voltage Vref

• 2s Complement Data Format

• Test Modes Which Include Digital Loopback and Analog Loopback

APPLICAONS

• Digital Still Cameras

• Wireless Accessories

• Hands-Free Car Kits

• VOIP

• Cable Modem