Dual J-K negative edge-triggered flip-flop
DESCRIPTION
The 74ALS112A, dual negative edge-triggered JK-type flip-flop features individual J, K, clock CPn, set SD, and reset RD inputs, true Qn and complementary Qn outputs.
The SD and RD inputs, when Low, set or reset the outputs as shown in the function table regardless of the level at the other inputs.
| 型号 | 品牌 | 下载 |
|---|---|---|
| 74ALS112AD | Philips 飞利浦 | 下载 |
| 74ALVC244PW,118 | NXP 恩智浦 | 下载 |
| 74ALVC164245DGG,11 | NXP 恩智浦 | 下载 |
| 74ALVC164245DL,118 | NXP 恩智浦 | 下载 |
| 74ALVC16244DGG | Philips 飞利浦 | 下载 |
| 74ALS08MX | Fairchild 飞兆/仙童 | 下载 |
| 74ALS245ASJX | Fairchild 飞兆/仙童 | 下载 |
| 74ALVCH16244DGG-T | NXP 恩智浦 | 下载 |
| 74ALVC164245DL | NXP 恩智浦 | 下载 |
| 74ALVC164245DGG | NXP 恩智浦 | 下载 |
| 74ALVCH162373ZQLR | TI 德州仪器 | 下载 |