SI5380A-B-GM

Si5380 无线抖动衰减时钟倍增器The Si5380 is a single chip Ultra Low Jitter, Any Frequency, 12-output JESD204B Clock Generator for 4G/LTE RRU. Integrated DSPLL technology simplifies design and PCB footprint together with removing the need for external VCXO, loop filter components and complex external filtering. Low phase noise JESD204B clock with interated LC-VCO. Highly immune to switching power supply noise and other noise sources. Simple and intuitive configuration with the ClockBuilder Pro software from Silicon Labs. Supported by the Si5380 Development Kit RS 8807317\- 支持 JESD204B 定时：DCLK 和 SYSREF \- 输入频率范围：10 MHz – 750 MHz \- 输出频率范围：480 kHz – 1.47456 GHz \- 极佳的抖动性能：80 fs typ 12 kHz – 20 MHz \- 相位噪声地板：–159 dBc/Hz \- 正齿性能：最大 –103 dBc（122.88 MHz 载频） \- 高度可配置输出，与 LVDS、LVPECL、LVCMOS、HCSL 和 CML 兼容，带可编程信号振幅 \- 4 输入、12 输出、64 引脚 QFN \- 温度范围：–40 至 +85 °C ### 时钟发生器/缓冲器

Si5380 无线抖动衰减时钟倍增器

The Si5380 is a single chip Ultra Low Jitter, Any Frequency, 12-output JESD204B Clock Generator for 4G/LTE RRU. Integrated DSPLL technology simplifies design and PCB footprint together with removing the need for external VCXO, loop filter components and complex external filtering.

Low phase noise JESD204B clock with interated LC-VCO.

Highly immune to switching power supply noise and other noise sources.

Simple and intuitive configuration with the ClockBuilder Pro software from .

Supported by the Si5380 Development Kit RS 8807317

\- 支持 JESD204B 定时：DCLK 和 SYSREF

\- 输入频率范围：10 MHz – 750 MHz

\- 输出频率范围：480 kHz – 1.47456 GHz

\- 极佳的抖动性能：80 fs typ 12 kHz – 20 MHz

\- 相位噪声地板：–159 dBc/Hz

\- 正齿性能：最大 –103 dBc（122.88 MHz 载频）

\- 高度可配置输出，与 LVDS、LVPECL、LVCMOS、HCSL 和 CML 兼容，带可编程信号振幅

\- 4 输入、12 输出、64 引脚 QFN

\- 温度范围：–40 至 +85 °C