与4 INTERGATED PAGES图文解码器 TELETEXT DECODER WITH 4 INTERGATED PAGES
DESCRIPTION
The is a HCMOS integrated circuit which performs all the processing of logical data within a 625 lines system teletext decoder.It is designed to operate in conjunction with one-chip: the SAA5231 integrated chip which extracts Teletext information embedded in a composite video signal. Up to 4 pages of display data can be stored in internal memory. A complete system also comprises a microprocessorcontrolling the STV5342 via a 2-wires serial bus. An on-chip ROM memory contains the character sets. The STV5342 performs automatic selection ofone of upto sixnaturallanguages.Data bytes may be decoded in either 7-Bit plus parity or in full 8-Bit formats. The chip set also supports facilities for reception and display of higher-level protocol data.
. COMPLETE TELETEXT DECODER INCLUDING ON-CHIP 4 PAGES MEMORY, REDUCING EMC RADIATIONS
. UPWARD SOFTWARE AND HARDWARE COMPATIBLE WITH PREVIOUS SGS-THOMSON’s DECODER SDA5243
. AUTOMATIC SELECTION OF UP TO SIX NATIONAL LANGUAGES
. 4 SIMULTANEOUS PAGE REQUESTS
. DISPLAY OF THE 25TH STATUS ROW
. MICROPROCESSOR CONTROL VIA AN I2C BUS SLAVE ADDRESS 0010001 R/W
. DATA ACQUISITION AVAILABLE FROM LINES 2 TO 22 OR FROM A COMPLETE FIELD
. HIGH QUALITY DISPLAY USING A CHARACTER MATRIX OF 12 x 10 DOTS
. SINGLE + 5V SUPPLY VOLTAGE
. ON-CHIP MASK PROGRAMMABLE ROM CHARACTER GENERATORS
. HCMOS PROCESS