AD9152BCPZRL

DAC 2CH Interpolation Filter 16Bit 56Pin LFCSP T/R

Product Details

The AD9152 is a dual, 16-bit, high dynamic range digital-to-analog converter DAC that provides a maximum sample rate of 2.25 GSPS, permitting a multicarrier generation up to the Nyquist frequency. The DAC outputs are optimized to interface seamlessly with the ADRF6720 analog quadrature modulator AQM from Analog Devices, Inc. An optional 3-wire or 4-wire serial port interface SPI provides for programming/readback of many internal parameters. The full-scale output current can be programmed over a range of 4 mA to 20 mA. The AD9152 is available in a 56-lead LFCSP. The AD9152 is a member of the TxDAC+® family.

**Product Highlights**

1. Ultrawide signal bandwidth enables emerging wideband and multiband wireless applications.

2. Advanced low spurious and distortion design techniques provide high quality synthesis of wideband signals from baseband to high intermediate frequencies.

3. JESD204B Subclass 1 support simplifies multichip synchronization in software and hardware design.

4. Fewer pins for data interface width with the serializer/deserializer SERDES JESD204B four-lane interface.

5. Programmable transmit enable function allows easy design balance between power consumption and wake-up time.

6. Small package size with an 8 mm × 8 mm footprint.

 

**Applications**

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Wireless communications

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Multicarrier LTE and GSM base stations

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Wideband repeaters

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Software defined radios

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Wideband communications

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Point to point microwave radios

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LMDS/MMDS

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Transmit diversity, multiple input/multiple output MIMO

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Instrumentation

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Automated test equipment

### Features and Benefits

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Supports input data rates up to 1.125 GSPS

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Proprietary low spurious and distortion design

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Single carrier LTE 20 MHz bandwidth BW, ACLR = 77 dBc

at 180 MHz IF

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SFDR = 72 dBc at 150 MHz IF, −6 dBFS

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Flexible 4-lane JESD204B interface

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Multiple chip synchronization

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Fixed latency

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Data generator latency compensation

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Selectable 1×, 2×, 4×, and 8× interpolation filter

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Low power architecture

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Input signal power detection

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Emergency stop for downstream analog circuitry protection

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Transmit enable function allows extra power saving

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High performance, low noise, phase-locked loop PLL clock multiplier

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Digital inverse sinc filter and programmable finite impulse response FIR filter

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Low power: 1223 mW at 1.5 GSPS, 1406 mW at 2.0 GSPS, full operating conditions

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56-lead LFCSP with exposed pad