ADATE304

200 MHz双通道集成DCL与电平设置的DAC ，每个引脚PMU和每个芯片VHH 200 MHz Dual Integrated DCL with Level Setting DACs, Per Pin PMU, and Per Chip VHH

Product Details

The is a complete, single-chip solution that performs the pin electronic functions of the driver, the comparator, and the active load DCL, per pin PMU, and dc levels for ATE applications. The device also contains an HVOUT driver with a VHH buffer capable of generating up to 13.5 V.

The driver features three active states: data high mode, data low mode, and term mode, as well as an inhibit state. The inhibit state, in conjunction with the integrated dynamic clamp, facilitates the implementation of a high speed active termination. The ADATE304 supports two output voltage ranges: −2.0 V to +6.0 V and −1.25 V to +6.75 V by adjusting the positive and negative supply voltages.

Each channel of the ADATE304 features a high speed window comparator per pin for functional testing, as well as a per pin PMU with FV, or FI and MV, or MI functions. All necessary dc levels for DCL functions are generated by on-chip 14-bit DACs. The per pin PMU features an on-chip 16-bit DAC for high accuracy and contains integrated range resistors to minimize external component counts.

The ADATE304 uses a serial bus to program all functional blocks and has an on-board temperature sensor for monitoring the device temperature.

**Applications**

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Automatic test equipment

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Semiconductor test systems

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Board test systems

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Instrumentation and characterization equipment

### Features and Benefits

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Driver

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3-level driver with high-Z mode and built-in clamps

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Precision trimmed output resistance

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Low leakage mode typically <10 nA

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Voltage range: −2.0 V to +6.0 V or −1.25 V to +6.75 V

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2.4 ns minimum pulse width, 2 V terminated

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Comparator

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Window and differential comparator

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500 MHz input equivalent bandwidth

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Load

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±12 mA maximum current capability

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Per pin PMU

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Force voltage range: −2.0 V to +6.0 V or −1.25 V to +6.75 V

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5 current ranges: 32 mA, 2 mA, 200 μA, 20 μA, 2 μA

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Levels

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14-bit DAC for DCL levels

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Typically < ±5 mV INL calibrated

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16-bit DAC for PMU levels

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Typically < ±1.5 mV INL calibrated linearity in FV mode

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HVOUT output buffer

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0 V to 13.5 V output range

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84-lead, 9 mm × 9 mm, CSP_BGA package

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900 mW per channel with no load