IS45S32400F-7BLA1

DRAM Chip SDRAM 128Mbit 4Mx32 3.3V Automotive 90Pin TFBGA

SDRAM 存储器 IC 128Mb（4M x 32） 并联 143 MHz 5.4 ns 90-TFBGA（8x13）

立创商城:
IS45S32400F 7BLA1

得捷:
IC DRAM 128MBIT PARALLEL 90TFBGA

艾睿:
DRAM Chip SDRAM 128Mbit 4Mx32 3.3V Automotive 90-Pin TFBGA

安富利:
ISSI"s 128Mb Synchronous DRAM achieves high-speed data transfer using pipeline architecture. All inputs and outputs signals the rising edge of the clock input. The 128Mb SDRAM is organized in 1Meg x 32 bit x 4 Banks.The 128Mb SDRAM is a high speed CMOS, dynamic random-access memory designed to operate in 3.3V Vdd and 3.3V Vddq memory systems containing 134,217,728 bits. Internally configured as a quad-bank DRAM with a synchronous interface. Each 33,554,432-bit bank is organized as 4,096 rows by 256 columns by 32 bits.The 128MbSDRAM includes an AUTOREFRESH MODE, and a power-saving, power-down mode. All signals are registered on the positive edge of the clock signal, CLK. All inputs and outputs are LVTTL compatible.The 128Mb SDRAM has the ability to synchronously burst data at a high data rate with automatic column-address generation, the ability to interleave between internal banks to hide precharge time and the capability to randomly change column addresses o