GS840H32AGB-100I

SRAM Chip Sync Quad 3.3V 4M-Bit 128K x 32 12ns/4.5ns 119Pin F-BGA Bulk

* FT pin for user-configurable flow through or pipelined operation * Single Cycle Deselect SCD operation * 3.3 V +10%/–5% core power supply * 2.5 V or 3.3 V I/O supply * LBO pin for Linear or Interleaved Burst mode * Internal input resistors on mode pins allow floating mode pins * Default to Interleaved Pipelined mode * Byte Write BW and/or Global Write GW operation * Common data inputs and data outputs * Clock control, registered, address, data, and control * Internal self-timed write cycle * Automatic power-down for portable applications * JEDEC standard 119-Bump BGA package * RoHS-compliant 100-lead TQFP and 119-Bump BGA packages * 2nd Generation