NXP 74HC573N 芯片, 74HC CMOS逻辑器件
The is an octal D-type Transparent Latch with 3-state is a high-speed Si-gate CMOS device and is pin compatible with low-power Schottky TTL LSTTL . It is specified in compliance with JEDEC standard no-7A. The octal D-type transparent latch featuring separate D-type inputs for each latch and 3-state true outputs for bus-oriented applications. A latch enable LE input and an output enable OE input are common to all latches. When LE is high, data at the Dn inputs enter the latches. In this condition the latches are transparent, i.e. a latch output will change state each time its corresponding D-input changes. When LE is low the latches store the information that was present at the D-inputs a set-up time preceding the high-to-low transition of LE. When OE is low, the contents of the 8-latches are available at the outputs. When OE is high, the outputs go to the high-impedance OFF-state. Operation of the OE input does not affect the state of the latches.
ESD sensitive device, take proper precaution while handling the device.