TEXAS INSTRUMENTS CD4029BE 芯片, 计数器/乘法器/除法器
The is a CMOS presettable Up/Down Counter consists of a four-stage binary or BCD-decade up/down counter with provisions for look-ahead carry in both counting modes. The inputs consist of a single Clock, Carry-In Clock Enable, Binary/Decade, Up/Down, Preset Enable and four individual JAN signals, Q1, Q2, Q3, Q4 and a carry out signal are provided as outputs. A high preset enable signal allows information on the jam inputs to preset the counter to any state asynchronously with the clock. A low on each JAM line, when the preset-enable signal is high, resets the counter to its zero count. The counter is advanced one count at the positive transition of the clock when the carry-in and preset enable signals are low. Advancement is inhibited when the carry-in or preset enable signals are high. The CARRY-OUT signal is normally high and goes low when the counter reaches its maximum count in the UP mode or the minimum count in the down mode provided the carry-in signal is low.