TMS320DM6435

TMS320DM6435 数字媒体处理器

The TMS320C64x+™ DSPs including the device are the highest-performance fixed-point DSP generation in the TMS320C6000™ DSP platform. The DM6435 device is based on the third-generation high-performance, advanced Veloci™ very-long-instruction-word VLIW architecture developed by Texas Instruments TI, making these DSPs an excellent choice for digital media applications. The C64x+™ devices are upward code-compatible from previous devices that are part of the C6000™ DSP platform. The C64x™ DSPs support added functionality and have an expanded instruction set from previous devices.

Any reference to the C64x DSP or C64x CPU also applies, unless otherwise noted, to the C64x+ DSP and C64x+ CPU, respectively.

With performance of up to 4800 million instructions per second MIPS at a clock rate of 600 MHz, the C64x+ core offers solutions to high-performance DSP programming challenges. The DSP core possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. The C64x+ DSP core processor has 64 general-purpose registers of 32-bit word length and eight highly independent functional units–two multipliers for a 32-bit result and six arithmetic logic units ALUs. The eight functional units include instructions to accelerate the performance in video and imaging applications. The DSP core can produce four 16-bit multiply-accumulates MACs per cycle for a total of 2400 million MACs per second MMACS, or eight 8-bit MACs per cycle for a total of 4800 MMACS. For more details on the C64x+ DSP, see the TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide literature number SPRU732.

The DM6435 also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals similar to the other C6000 DSP platform devices. The DM6435 core uses a two-level cache-based architecture. The Level 1 program memory/cache L1P consists of a 256K-bit memory space that can be configured as mapped memory or direct mapped cache, and the Level 1 data L1D consists of a 640K-bit memory space–384K-bit of which is mapped memory and 256K-bit of which can be configured as mapped memory or 2-way set-associative cache. The Level 2 memory/cache L2 consists of a 1M-bit memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or combinations of the two.

The peripheral set includes: a configurable video port VPFE; a 10/100 Mb/s Ethernet MAC EMAC with a management data input/output MDIO module; a 4-bit transmit, 4-bit receive VLYNQ interface; an inter-integrated circuit I2C Bus interface; a multichannel buffered serial port McBSP; a multichannel audio serial port McASP0 with 4 serializers; 2 64-bit general-purpose timers each configurable as 2 independent 32-bit timers; 1 64-bit watchdog timer; a user-configurable 16-bit host-port interface HPI; up to 111-pins of general-purpose input/output GPIO with programmable interrupt/event generation modes, multiplexed with other peripherals; 2 UARTs with hardware handshaking support on 1 UART; 3 pulse width modulator PWM peripherals; 1 high-end controller area network CAN controller [HECC]; and 2 glueless external memory interfaces: an asynchronous external memory interface EMIFA for slower memories/peripherals, and a higher speed synchronous memory interface for DDR2.

The DM6435 device includes a Video Processing Subsystem VPSS with a configurable video/imaging front-end input peripheral used for video capture.

The Video Processing Front-End VPFE is comprised of a CCD Controller CCDC, a Preview Engine Previewer, Histogram Module, Auto-Exposure/White Balance/Focus Module H3A, and Resizer. The CCDC is capable of interfacing to common video decoders, CMOS sensors, and Charge Coupled Devices CCDs. The Previewer is a real-time image processing engine that takes raw imager data from a CMOS sensor or CCD and converts from an RGB Bayer Pattern to YUV422. The Histogram and H3A modules provide statistical information on the raw color data for use by the DM6435. The Resizer accepts image data for separate horizontal and vertical resizing from 1/4x to 4x in increments of 256/N, where N is between 64 and 1024.

The Ethernet Media Access Controller EMAC provides an efficient interface between the DM6435 and the network. The DM6435 EMAC support both 10Base-T and 100Base-TX, or 10 Mbits/second Mbps and 100 Mbps in either half- or full-duplex mode, with hardware flow control and quality of service QOS support.

The Management Data Input/Output MDIO module continuously polls all 32 MDIO addresses in order to enumerate all PHY devices in the system.

The I2C and VLYNQ ports allow DM6435 to easily control peripheral devices and/or communicate with host processors.

The high-end controller area network CAN controller [HECC] module provides a network protocol in a harsh environment to communicate serially with other controllers, typically in automotive applications.

The rich peripheral set provides the ability to control external peripheral devices and communicate with external processors. For details on each of the peripherals, see the related sections later in this document and the associated peripheral reference guides.

The DM6435 has a complete set of development tools. These include C compilers, a DSP assembly optimizer to simplify programming and scheduling, and a Windows™ debugger interface for visibility into source code execution.

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High-Performance Digital Media Processor DM6435

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2.5-, 2-, 1.67, 1.51-, 1.43-ns Instruction Cycle Time

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400-, 500-, 600-, 660-, 700-MHz C64x+™ Clock Rate

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Eight 32-Bit C64x+ Instructions/Cycle

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3200, 4000, 4800, 5280, 5600 MIPS

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Fully Software-Compatible With C64x

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Commercial and Automotive Q or S suffix Grades

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Low-Power Device L suffix

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VelociTI.2™ Extensions to VelociTI™ Advanced Very-Long-Instruction-Word VLIW TMS320C64x+™ DSP Core

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Eight Highly Independent Functional Units With VelociTI.2 Extensions:

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Six ALUs 32-/40-Bit, Each Supports Single 32-Bit, Dual 16-Bit, or Quad 8-Bit Arithmetic per Clock Cycle

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Two Multipliers Support Four 16 × 16-Bit Multiplies 32-Bit Results per Clock Cycle or Eight 8 × 8-Bit Multiplies 16-Bit Results per Clock Cycle

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Load-Store Architecture With Non-Aligned Support

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64 32-Bit General-Purpose Registers

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Instruction Packing Reduces Code Size

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All Instructions Conditional

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Additional C64x+™ Enhancements

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Protected Mode Operation

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Exceptions Support for Error Detection and Program Redirection

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Hardware Support for Modulo Loop Auto-Focus Module Operation

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C64x+ Instruction Set Features

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Byte-Addressable 8-/16-/32-/64-Bit Data

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8-Bit Overflow Protection

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Bit-Field Extract, Set, Clear

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Normalization, Saturation, Bit-Counting

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VelociTI.2 Increased Orthogonality

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C64x+ Extensions

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Compact 16-bit Instructions

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Additional Instructions to Support Complex Multiplies

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C64x+ L1/L2 Memory Architecture

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256K-Bit 32K-Byte L1P Program RAM/Cache [Flexible Allocation]

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640K-Bit 80K-Byte L1D Data RAM/Cache [Flexible Allocation]

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1M-Bit 128K-Byte L2 Unified Mapped RAM/Cache [Flexible Allocation]

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Supports Little Endian Mode Only

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Video Processing Subsystem VPSS, VPFE Only

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Front End Provides:

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CCD and CMOS Imager Interface

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BT.601/BT.656 Digital YCbCr 4:2:2 8-/16-Bit Interface

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Preview Engine for Real-Time Image Processing

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Glueless Interface to Common Video Decoders

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Histogram Module

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Auto-Exposure, Auto-White Balance and Auto-Focus Module

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Resize Engine

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Resize Images From 1/4× to 4×

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Separate Horizontal/Vertical Control

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External Memory Interfaces EMIFs

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32-Bit DDR2 SDRAM Memory Controller With 256M-Byte Address Space 1.8-V I/O

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Supports up to 333-MHz data rate bus and interfaces to DDR2-400 SDRAM

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Asynchronous 8-Bit Wide EMIF EMIFA With up to 64M-Byte Address Reach

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Flash Memory Interfaces

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NOR 8-Bit-Wide Data

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NAND 8-Bit-Wide Data

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Enhanced Direct-Memory-Access EDMA Controller 64 Independent Channels

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Two 64-Bit General-Purpose Timers Each Configurable as Two 32-Bit Timers

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One 64-Bit Watch Dog Timer

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Two UARTs One with RTS and CTS Flow Control

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Master/Slave Inter-Integrated Circuit I2C Bus™

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Multichannel Buffered Serial Port McBSP

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I2S and TDM

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AC97 Audio Codec Interface

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SPI

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Standard Voice Codec Interface AIC12

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Telecom Interfaces - ST-Bus, H-100

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128 Channel Mode

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Multichannel Audio Serial Port McASP0

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Four Serializers and SPDIF DIT Mode

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16-Bit Host-Port Interface HPI

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High-End CAN Controller HECC

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10/100 Mb/s Ethernet MAC EMAC

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IEEE 802.3 Compliant

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Supports Media Independent Interface MII

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Management Data I/O MDIO Module

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VLYNQ™ Interface FPGA Interface

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Three Pulse Width Modulator PWM Outputs

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On-Chip ROM Bootloader

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Individual Power-Savings Modes

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Flexible PLL Clock Generators

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IEEE-1149.1 JTAG™ Boundary-Scan-Compatible

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Up to 111 General-Purpose I/O GPIO Pins Multiplexed With Other Device Functions

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Packages:

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361-Pin Pb-Free PBGA Package ZWT Suffix, 0.8-mm Ball Pitch

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376-Pin Plastic BGA Package ZDU Suffix, 1.0-mm Ball Pitch

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0.09-µm/6-Level Cu Metal Process CMOS

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3.3-V and 1.8-V I/O, 1.2-V Internal -7/-6/-5/-4/-L/-Q6/-5Q/-4Q

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3.3-V and 1.8-V I/O, 1.05-V Internal -7/-6/-5/-4/-L/-Q5

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Applications:

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Digital Media

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* Networked Media Encode

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Video Imaging

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