可编程27位串行到并行接收 PROGRAMMABLE 27-BIT SERIAL-TO-PARALLEL RECEIVER
The receiver de-serializes FlatLink™3G compliant serial input data to 27 parallel data outputs. The SN65LVDS302 receiver contains one shift register to load 30 bits from 1, 2 or 3 serial inputs and latches the 24 pixel bits and 3 control bits out to the parallel CMOS outputs after checking the parity bit. If the parity check confirms correct parity, the Channel Parity Error CPE output remains low. If a parity error is detected, the CPE output generates a high pulse while the data output bus disregards the newly-received pixel. Instead, the last data word is held on the output bus for another clock cycle.
SN65LVDS301
and 3 Control Bits Received over 1, 2 or 3
SubLVDS Differential Lines
µBGA® With 0.5-mm Ball Pitch
型号 | 品牌 | 下载 |
---|---|---|
SN65LVDS302 | TI 德州仪器 | 下载 |
SN65LVDS2DBV | TI 德州仪器 | 下载 |
SN65240PW | TI 德州仪器 | 下载 |
SN65240PWG4 | TI 德州仪器 | 下载 |
SN65240PWRG4 | TI 德州仪器 | 下载 |
SN65220DBVTG4 | TI 德州仪器 | 下载 |
SN65240P | TI 德州仪器 | 下载 |
SN65240PE4 | TI 德州仪器 | 下载 |
SN65LVDS32BDR | TI 德州仪器 | 下载 |
SN65LVDS2DBVR | TI 德州仪器 | 下载 |
SN65LVDS2DBVT | TI 德州仪器 | 下载 |