SN65LVDS302

可编程27位串行到并行接收 PROGRAMMABLE 27-BIT SERIAL-TO-PARALLEL RECEIVER

The receiver de-serializes FlatLink™3G compliant serial input data to 27 parallel data outputs. The SN65LVDS302 receiver contains one shift register to load 30 bits from 1, 2 or 3 serial inputs and latches the 24 pixel bits and 3 control bits out to the parallel CMOS outputs after checking the parity bit. If the parity check confirms correct parity, the Channel Parity Error CPE output remains low. If a parity error is detected, the CPE output generates a high pulse while the data output bus disregards the newly-received pixel. Instead, the last data word is held on the output bus for another clock cycle.

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Serial Interface Technology

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Compatible With FlatLink™3G such as

SN65LVDS301

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Supports Video Interfaces up to 24-bit RGB Data

and 3 Control Bits Received over 1, 2 or 3

SubLVDS Differential Lines

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SubLVDS Differential Voltage Levels

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Up to 1.755-Gbps Data Throughput

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Three Operating Modes to Conserve Power

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Active mode QVGA: 17 mW

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Typical Shutdown: 0.7 µW

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Typical Standby Mode: 27 µW Typical

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Bus-Swap Function for PCB-Layout Flexibility

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ESD Rating > 4 kV HBM

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Pixel Clock Range of 4 MHz to 65 MHz

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Failsafe on all CMOS Inputs

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Packaged in 5-mm × 5-mm MicroStar Junior

µBGA® With 0.5-mm Ball Pitch

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Very low EMI meets SAE J1752/3 ′Kh′-spec