ADF4356BCPZ-RL7

Clock Generator 10MHz to 600MHz Input 6800MHz Output 1 32Pin LFCSP EP T/R

Product Details

The ADF4356 allows implementation of fractional-N or integer-N phase-locked loop PLL frequency synthesizers when used with an external loop filter and an external reference frequency. A series of frequency dividers at another frequency output permits operation from 53.125 MHz to 6800 MHz.

The ADF4356 has an integrated VCO with a fundamental output frequency ranging from 3400 MHz to 6800 MHz. In addition, the VCO frequency is connected to divide by 1, 2, 4, 8, 16, 32, or 64 circuits that allow the user to generate RF output frequencies as low as 53.125 MHz. For applications that require isolation, the RF output stage can be muted. The mute function is both pin- and software-controllable.

Control of all on-chip registers is through a simple 3-wire interface. The ADF4356 operates with analog and digital power supplies ranging from 3.15 V to 3.45 V, with charge pump and VCO supplies from 4.75 V to 5.25 V. The ADF4356 also contains hardware and software power-down modes.

Applications

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Wireless infrastructure LTE, W-CDMA, TD-SCDMA, WiMAX, GSM, PCS, DCS

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Point to point/point to multipoint microwave links

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Satellites/VSATs

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Test equipment/instrumentation

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Clock generation

### Features and Benefits

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RF output frequency range: 53.125 MHz to 6800 MHz

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Integer channel: −227 dBc/Hz

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Fractional channel: −225 dBc/Hz

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Integrated RMS jitter 1 kHz to 20 MHz: 97 fs for 6 GHz output

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Fractional-N synthesizer and integer-N synthesizer

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Pin compatible to the ADF4355

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High resolution, 52-bit modulus

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Phase frequency detector PFD operation to 125 MHz

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Reference input frequency operation to 600 MHz

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Maintains frequency lock over −40°C to +85°C

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Low phase noise, voltage controlled oscillator VCO

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Programmable divide by 1, 2, 4, 8, 16, 32, or 64 output

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Analog and digital power supplies: 3.3 V

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Charge pump and VCO power supplies: 5.0 V typical

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Logic compatibility: 1.8 V

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Programmable output power level

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RF output mute function

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Supported in the simPLL design tool