IS43R16160B-6TL

INTEGRATED SILICON SOLUTION ISSI  IS43R16160B-6TL  存储芯片, SDRAM, DDR, 16M X 16, 2.5V, 66TSOP2

The is a 256MB DDR Synchronous DRAM 4-bank x 4194304-word x 16-bit double data rate synchronous DRAM with SSTL-2 interface. All control and address signals are referenced to the rising edge of CLK. Input data is registered on both edges of data strobe and output data and data strobe are referenced on both edges of CLK. The device achieves very high speed clock rate up to 200MHz.

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Double data rate architecture; two data transfers per clock cycle

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Bidirectional, data strobe DQS is transmitted/received with data

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Differential clock input

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DLL aligns DQ and DQS transitions with CLK transitions edges of DQS

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Commands entered on each positive CLK edge

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Data and data mask referenced to both edges of DQS

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4 Bank operation controlled by BA0, BA1

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Auto pre-charge/all bank pre-charge controlled by A10

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8192 Refresh cycles/64ms

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Auto refresh and self refresh

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Row address A0-12/column address A0-9/A0-8

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SSTL_2 interface

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Speed - 6ns