PCA9516AD

NXP  PCA9516AD  芯片, 总线集线器, I2C, 5通道, 16SOIC

The is a 5-channel CMOS I²C-Bus Hub intended for application in I²C-bus and SMBus systems. While retaining all the operating modes and features of the I²C-bus system, it permits extension of the I²C-bus by buffering both the data SDAn and the clock SCLn lines, thus enabling five buses of 400pF. The I²C-bus capacitance limit of 400pF restricts the number of devices and bus length. Using the bus hub enables the system designer to divide the bus into five segments off of a hub where any segment-to-segment transition sees only one repeater delay.

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5-channel, bidirectional buffer

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Active high individual repeater enable input

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Open-drain input/outputs

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Lock-up free operation

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Supports arbitration and clock stretching across the repeater

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Powered-off high-impedance I²C pins

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Latch-up testing is done to JEDEC standard JESD78 which exceeds 100mA