AS8C401801-QC166N

AS8C401801 系列 4 Mb 256 K x 18 3.3 V 3.5 ns 同步 RAM - TQFP100

SRAM - 同步，SDR 存储器 IC 4Mb（256K x 18） 并联 166 MHz 3.5 ns 100-TQFP（14x20）

得捷:
IC SRAM 4MBIT PARALLEL 100TQFP

贸泽:
SRAM 4M, 3.3V, 166MHz 256K x 18 Synch SRAM

安富利:
The 401801 is a 3.3V high-speed 4,718,592-bit 4.5 Mega-bit synchronous SRAMS. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus, it has been given the name ZBTTM, or Zero Bus Turnaround.Address and control signals are applied to the SRAM during one clock cycle, and two cycles later the associated data cycle occurs, be it read or write.The 401801 contain data I/O, address and control signal registers. Output enable is the only asynchronous signal and can be used to disable the outputs at any given time.A Clock Enable CEN pin allows operation of the 401801 to be suspended as long as necessary. All synchronous inputs are ignored when CEN is high and the internal device registers will hold their previous values.There are three chip enable pins CD , CE2, CE2 that allow the user to deselect the device when desired. If any one of these three are not asserted when ADV/LD is low, no new memory operation can be initiated. However, any pending data transfers reads or writes will be completed. The data bus will tri-state two cycles after chip is deselected or a write is initiated.

TME:
Memory; SRAM, synchronous; 256x18bit; 3÷3.6V; 166ns; TQFP100