MC100EP210SFAG

ON SEMICONDUCTOR  MC100EP210SFAG  CLOCK DRIVER, DUAL, 1GHZ, LQFP-32 新

The MC100EP210S is a low skew 1-to-5 dual differential driver, designed with LVDS clock distribution in mind. The LVDS or LVPECL input signals are differential and the signal is fanned out to five identical differential LVDS outputs. The EP210S specifically guarantees low output-to-output skew. Optimal design, layout, and processing minimize skew within a device and from device to device. Two internal 50-ohm resistors are provided across the inputs. For LVDS inputs, VTA and VTB pins should be unconnected. For LVPECL inputs, VTA and VTB pins should be connected to the V Designers can take advantage of the EP210S performance to distribute low skew LVDS clocks across the backplane or the board. Special considerations are required for differential inputs under No Signal conditions to prevent instability.

Features

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20 ps Typical Output-to-Output Skew

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85 ps Typical Device-to-Device Skew

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550 ps Typical Propagation Delay

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The 100 Series contains temperature compensation.

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Maximum Frequency > 1 Ghz

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Operating Range: VCC = 2.375 V to 2.625 V with VEE = 0 V

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Internal 50Ω Input Termination Resistors

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LVDS Input/Output Compatible

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Pb-Free Packages are Available