IS43LR32160C-6BLI

INTEGRATED SILICON SOLUTION ISSI  IS43LR32160C-6BLI  芯片, 存储器, SDRAM, DDR3, 512MB, 166MHZ, BGA-90

The is a 536870912-bit CMOS Mobile Double Data Rate Synchronous DRAM organized as 4 banks of 4194304 words x 32-bit. This product uses a double-data-rate architecture to achieve high-speed operation. The data input/output signals are transmitted on a 32-bit bus. The double data rate architecture is essentially a 2N pre-fetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. This product offers fully synchronous operations referenced to both rising and falling edges of the clock. The data paths are internally pipelined and 2n-bit pre-fetched to achieve very high bandwidth. All input and output voltage levels are compatible with LVCMOS.

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JEDEC standard 1.8V power supply

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4-Internal banks for concurrent operation

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MRS cycle with address key programs

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Fully differential clock inputs

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All inputs except data & DM are sampled at the rising edge of the system clock

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Data I/O transaction on both edges of data strobe

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Bidirectional data strobe per byte of data

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DM for write masking only

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Edge aligned data and data strobe output

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Center aligned data and data strobe input

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64ms Refresh period

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Auto and self refresh

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Concurrent auto pre-charge

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Maximum clock frequency up to 200MHz

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Maximum data rate up to 400Mbps/pin

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Power saving support

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Status register read

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LVCMOS compatible inputs/outputs