74LVT573PW,118

NXP  74LVT573PW,118  芯片, 锁存器, D型, 透明, 三态, TSSOP-20

The 74LVT573PW is an octal BiCMOS transparent D Latch designed for VCC operation at 3.3V. It is coupled to eight 3-state output buffers. The two sections of the device are controlled independently by LE and OE\ control gates. It has a broadside pinout configuration to facilitate PC board layout and allow easy interface with microprocessors. The data on the Dn inputs are transferred to the latch outputs when the LE input is high. The latch remains transparent to the data inputs while LE is high and stores the data that is present one setup time before the high-to-low enable transition. The 3-state output buffers are designed to drive heavily loaded 3-state buses, MOS memories or MOS microprocessors. The active-low OE\ controls all eight 3-state buffers independent of the latch operation. When OE\ is low, the latched or transparent data appears at the outputs.

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Inputs and outputs arranged for easy interfacing to microprocessors

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3-state outputs for bus interfacing

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Common output enable control

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TTL input and output switching levels

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Input and output interface capability to systems at 5V supply

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Bus hold data inputs eliminate need for external pull-up resistors to hold unused inputs

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Live insertion and extraction permitted

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No bus current loading when output is tied to 5V bus

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Power-up reset

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Power-up 3-state

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Latch-up protection