SRAM Chip Sync Dual 3.3V 9M-bit 512K x 18 7.5ns 100Pin TQFP
* 100 percent bus utilization * No wait cycles between Read and Write * Internal self-timed write cycle * Individual Byte Write Control * Single Read/Write control pin * Clock controlled, registered address, data and control * Interleaved or linear burst sequence control using MODE input * Three chip enables for simple depth expansion and address pipelining * Power Down mode * Common data inputs and data outputs * CKE pin to enable clock and suspend operation * JEDEC 165-ball PBGA package * Power Supply: Vdd 2.5V ± 5%, Vddq 2.5V ± 5% * JTAG Boundary Scan for PBGA packages * Commercial and Industrial temperature available * Lead-free available.
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