NXP 74HC93N 芯片, 74HC CMOS逻辑器件
The is a 4-bit binary Ripple Counter pin compatible with low power Schottky TTL LSTTL. It consists of four master-slave flip-flops internally connected to provide a divide-by-two section and a divide-by-eight section. Each section has a separate clock input CP0\ and CP1\\ to initiate state changes of the counter on the high-to-low clock transition. State changes of the Qn outputs do not occur simultaneously because of internal ripple delays. Therefore, decoded output signals are subject to decoding spikes and should not be used for clocks or strobes. A gated AND asynchronous master reset MR1 and MR2 is provided which overrides both clocks and resets clears all flip-flops. Since the output from the divide-by-two section is not internally connected to the succeeding stages, the device may be operated in various counting modes. In a 4-bit ripple counter the output Q0 must be connected externally to input CP1\\.