Scan rate converter using embedded DRAM technology unit
General description
The SDA 9400 is a new component of the MEGAVISION® IC set in a 0.35 µm embedded DRAM technology frame memory embedded. The SDA 9400 is pin compatible to the SDA 9401 field memory embedded. The SDA 9400 comprises all main functionalities of a digital featurebox in one monolithic IC.
Features
• Two input data formats
\- 4:2:2 luminance and chrominance parallel 2 x 8 wires
\- ITU-R 656 data format 8 wires
• Two different representations of input chrominance data
\- 2‘s complement code
\- Positive dual code
• Flexible input sync controller
• Flexible compression of the input signal
\- Digital vertical compression of the input signal 1.0, 1.25, 1.5, 1.75, 2.0, 3.0, 4.0
\- Digital horizontal compression of the input signal 1.0, 2.0, 4.0
• Noise reduction
\- Motion adaptive spatial and temporal noise reduction 3D-NR
\- Temporal noise reduction for luminance frame based or field based
\- Temporal noise reduction for chrominance field based
\- Separate motion detectors for luminance and chrominance
\- Flexible programming of the temporal noise reduction parameters
\- Automatic measurement of the noise level 5 bit value, readable by I²C bus
• 3-D motion detection
\- High performance motion detector for scan rate conversion
\- Global motion detection flag readable by I²C bus
\- Movie mode and phase detector readable by I²C bus