SN74LV20A

双路 4 输入正与非门

These dual 4-input positive-NAND gates are designed for 2-V to 5.5-V VCC operation.

The "LV20A devices perform the Boolean function Y = A • B • C • D\ or Y = A\ + B\ + C\ + D\ in positive logic.

These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down.

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2-V to 5.5-V VCC Operation

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Max tpd of 6 ns at 5 V

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Typical VOLP Output Ground Bounce

    <0.8 V at VCC = 3.3 V, TA = 25°C

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Typical VOHV Output VOH Undershoot

   >>2.3 V at VCC = 3.3 V, TA = 25°C

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Ioff Supports Partial-Power-Down Mode Operation

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Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II

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ESD Protection Exceeds JESD 22

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2000-V Human-Body Model A114-A

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200-V Machine Model A115-A

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1000-V Charged-Device Model C101