AD6676BCBZRL

RF Receiver 1.1V/2.5V 80Pin WLCSP T/R

Product Details

### For a limited time, take a live test drive of the AD6676 by using our remote evaluation software.

The AD6676 is a highly integrated IF subsystem that can digitize radio frequency RF bands up to 160 MHz in width centered on an intermediate frequency IF of 70 MHz to 450 MHz. Unlike traditional Nyquist IF sampling ADCs, the AD6676 relies on a tunable band-pass Σ-Δ ADC with a high oversampling ratio to eliminate the need for band specific IF SAW filters and gain stages, resulting in significant simplification of the wideband radio receiver architecture. On-chip quadrature digital downconversion followed by selectable decimation filters reduces the complex data rate to a manageable rate between 62.5 MSPS to 266.7 MSPS. The 16-bit complex output data is transferred to the host via a single or dual lane JESD204B interface supporting line rates of up to 5.333 Gbps.

Applications

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Wideband cellular infrastructure equipment and repeaters 

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Point-to-point microwave equipment 

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Instrumentation 

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Spectrum and communication analyzers 

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Software defined radio

### Features and Benefits

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High instantaneous dynamic range

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Noise figure NF as low as 13 dB

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Noise spectral density NSD as low as −159 dBFS/Hz

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IIP3 up to 36.9 dBm with spurious tones <−99 dBFS

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Tunable band-pass Σ-Δ analog-to-digital converter ADC

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20 MHz to 160 MHz signal bandwidth

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70 MHz to 450 MHz IF center frequency

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Configurable input full-scale level of −2 dBm to −14 dBm

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Easy to drive resistive IF input

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Gain flatness of 1 dB with under 0.5 dB out-of-band peaking

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Alias rejection greater than 50 dB

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2.0 GSPS to 3.2 GSPS ADC clock rate

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On-chip PLL clock multiplier

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16-bit I/Q rate up to 266 MSPS

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On-chip digital signal processing

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NCO and quadrature digital downconverter QDDC

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Selectable decimation factor of 12, 16, 24, and 32

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Automatic gain control AGC support

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On-chip attenuator with 27 dB span in 1 dB steps

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Fast attenuator control via configurable AGC data port 

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Peak detection flags with programmable thresholds

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Single or dual lane, JESD204B capable

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Low power consumption: 1.20 W

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1.1 V and 2.5 V supply voltage

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TDD power saving up to 60%

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4.3 mm × 5.0 mm WLCSP