EP20K200BC356-1X

FPGA - 现场可编程门阵列 CPLD - APEX 20K 832 Macro 277 IOs

* 200K Typical gates * 8320 logic elements LEs * MultiCoreTM architecture integrating look-up table LUT logic, product-term logic, and embedded memory * LUT logic used for register-intensive functions * Embedded system block ESB used to implement memory functions, including first-in first-out FIFO buffers, dual-port RAM, and content-addressable memory CAM * ESB implementation of product-term logic used for combinatorial-intensive functions * Built-in low-skew clock tree * Up to eight global clock signals * LVDS performance up to 840 Mbits per channel * Programmable output slew-rate control to reduce switching noise * Quartus II SignalTap® embedded logic analyzer simplifies in-system design evaluation by giving access to internal nodes during device operation